Hey guys,
So I've got a simple component that manipulates two std_logic_vector inputs into one.
The behaviour of this component should be that where N=4. The output Y is constructed by interleaving the bits of A and B together as shown in the table below....
VHDL N-Bit Interleave explanation?
So I've got a simple component that manipulates two std_logic_vector inputs into one.
Code (Text):
- entity interleave is
- generic (
- N : natural := 4
- );
- port(
- A : in std_logic_vector((N-1) downto 0);
- B : in std_logic_vector((N-1) downto 0);
- Y : out std_logic_vector((2*N-1) downto 0)
- );
- end entity;
VHDL N-Bit Interleave explanation?