What is the clock generating diagram I2C protocol while sending Data & Address from mater to slave.

I need to communicate between Micro controller & FPGA(frame grabber card) using I2C protocol.
I want to know if data 5 has been sent from Master (Controller) what will be the clock generation.
Using clock generation i can set frame grabber card as readable.

Is this possible or can we determine the I2C clock cycle generated?